The present application relates to semiconductor technology and more particularly to a method of forming dual channel complementary metal oxide semiconductor (CMOS) field effect transistors (i.e., FETs) on a same substrate. The present application also relates to a semiconductor structure that can be formed by the method.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
Dual channel CMOS having different semiconductor channel materials is needed for 10 nm and beyond technologies. For example, III-V compound semiconductor channel materials are needed for nFET devices, while germanium-containing semiconductor channel materials are needed for pFET devices. Aspect ratio trapping (ART) is an effective way to grow semiconductor materials on a semiconductor wafer and thus can be used for providing a structure having different semiconductor materials. Conventional ART however has some drawbacks that are associated therewith. For example, conventional ART can be used in providing thin semiconductor fin structures, but it is difficult to form large planar structures.
Moreover and in conventional ART, a defect-containing semiconductor material portion of the ART grown semiconductor material remains in the structure after ART growth. The defect-containing semiconductor material portion of the ART grown semiconductor material must be isolated from the semiconductor material portion of the ART grown semiconductor material or it will cause excessive device leakage.
In view of the above, there is a need for providing dual channel CMOS having different semiconductor channel materials, e.g., a III-V compound semiconductor channel material for nFETs and a germanium-containing channel material for pFETs, that avoids the drawbacks mentioned above.